View PEB2096_1039353.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ICs for Communications
Octal Transceiver for UPN Interfaces OCTAT-P PEB 2096 Version 1.3
Data Sheet 01.96
T2096-V13-D2-7600
PEB 2096 Revision History: Previous Version: Page (in Version 11.93) Page (in new Version) 17 18 22 26 30 48 37 39 42 50 53 58 60
Current Version: 01.96 Technical Manual 11.93 Subjects (major changes since last revision)
New description of synchronization to the DCL frequency New Version 1.3 number New description of loop length New description of the transmit delay on UPN interface in respect to IOM-2 interface New bit in the Configuration Register for UPN Line Interfaces: EQUDIS Changed DC characteristics on LIna,b Better jitter description Changed SSYNC timing New description of UPN frame relation to FSC
Edition 01.96 This edition was realized using the software system FrameMaker(R). Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen
(c)
Siemens AG 1996. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
PEB 2096
Table of Contents 1 1.1 1.2 1.3 1.4 1.5 2 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.3.1 2.2.3.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 3 3.1 3.2 3.3 3.4 3.5 3.5.1 3.5.2 3.6 3.7 3.8 3.9 3.9.1 3.9.2 3.9.3 4 4.1 4.2 4.3 4.4
Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 General Principle of the UPN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 IOM(R)-2 System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 JTAG Boundary Scan Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Boundary Scan Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Individual Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Transceiver, Analog Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Transmit PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Receive PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Receive Signal Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Activation / Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Clocking, Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Push - Pull Sensing on Pin DU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Transmit Delay on UPN Interface in respect to IOM(R)-2 Interface . . . . . . . . . .30 UPN Multiframe Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Synchronization with a Short FSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Synchronization using SSYNC (for DECT) . . . . . . . . . . . . . . . . . . . . . . . . . .31 D-Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 IOM(R)-2 Interface Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Command / Indicate Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Activation and Deactivation, State Machine . . . . . . . . . . . . . . . . . . . . . . . . . .40 States Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Info Structure on the UPN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Example of Activation and Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Identification Register - (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 General Configuration Register - (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Bit Error Register - (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Configuration Register for UPN Line Interfaces - (Write) . . . . . . . . . . . . . . . .48
3 01.96
Semiconductor Group
PEB 2096
Table of Contents 4.5 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6
Page
Test Registers - (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Timing of the IOM(R) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 UPN Frame Relation to FSC in Transmit Direction . . . . . . . . . . . . . . . . . . . . .60 Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
IOM(R), IOM(R)-1, IOM(R)-2, SICOFI(R), SICOFI(R)-2, SICOFI(R)-4, SICOFI(R)-4C, SLICOFI(R), ARCOFI(R) , ARCOFI(R)-BA, ARCOFI(R)-SP, EPIC(R)-1, EPIC(R)-S, ELIC(R), IPAT(R)-2, ITAC(R), ISAC(R)-S, ISAC(R)-S TE, ISAC(R)-P, ISAC(R)-P TE, IDEC(R), SICAT(R), OCTAT(R)-P, QUAT(R)-S are registered trademarks of Siemens AG. MUSACTM-A, FALCTM54, IWETM, SARETM, UTPTTM, ASMTM, ASPTM are trademarks of Siemens AG. Purchase of Siemens I2C components conveys a license under the Philips' I2C patent to use the components in the I2C-system provided the system conforms to the I2C specifications defined by Philips. Copyright Philips 1983.
Semiconductor Group
4
01.96
PEB 2096
1
Overview
A Line Card or a PBX consists of a line card controller, multiple layer-1 transceivers for t/r (a/b), S/T, UP and U2B1Q interfaces, signaling controllers, a microprocessor, memory, power supply, transformers, etc. The new Siemens generation of highly integrated ISDN circuits enables design Engineers to decrease board size and thus PBX size and its production costs. Figure 1 shows an example of a PBX for up to 16 ISDN and 16 analog subscribers with 4 trunk lines realized with a few highly integrated chips of the new Siemens family of PBX and Line Cards ICs: ELIC, SICOFI-4, OCTAT-P, QUAT-S and IDEC. ELIC, Enhanced Line Card Controller, PEB 20550, comprises the following functional blocks on a single chip: * Extended PCM Interface Controller (EPIC-1), which can switch up to 32 digital (ISDN) or 64 voice (analog) subscribers, * Two HDLC interface controllers (SACCO-A and SACCO-B), * One D-channel arbiter to multiplex one HDLC controller (SACCO-A) to multiple subscribers. The ELIC is a CMOS device offered in a P-MQFP-64 package. OCTAT-P The Octal Transceiver for UPN interfaces, PEB 2096, implements the two-wire UPN interface used to link voice/data digital terminals to PBX subscriber lines. The OCTAT-P is an optimized device for LT applications and can handle up to eight UPN interfaces simultaneously. It handles the UPN interfaces in accordance with the UP0 interface specification except for the reduced loop length. The OCTAT-P is a CMOS device offered in a P-MQFP-44 package. QUAT-S The Quadruple Transceiver for S/T Interfaces, PEB 2084, implements 4 four-wire S/T interfaces to link voice/data digital terminals to PBX subscriber lines or PBX trunk lines to the public ISDN. It can handle up to four S/T interfaces simultaneously in accordance with CCITT I.430, ETSI 300.012, and ANSI T1.605 standards. The QUAT-S is a CMOS device offered in a P-MQFP-44 package. IDEC The ISDN D-Channel Exchange Controller, PEB 2075, is an HDLC controller which handles four HDLC communication channels. Each channel is fully independent and programmable by its own register set. The IDEC is a CMOS device offered in a P-LCC-44 and P-DIP-28 package.
Semiconductor Group
5
01.96
PEB 2096
IOM -2 2048 kbit/s
TE 0 8xS TE 7 TE 0 8 x U PN TE 7 U PN S0 QUAT-S PEB 2084 CFI 0
R
R
PCM 0
PCM
ELIC PEB 20550 OCTAT -P PEB 2096
R
1
D Arbiter TE 1 16 x t/r TE 16 SLIC r/t SLIC 2 SICOFI -4 PEB 2465 3 TSS SACCO-B Signaling 8xT 0 CO 7
R
SACCO-A
Memory
IOM -2
R
QUAT-S PEB 2084
P Interface
P
IOM -2
R
4 x D Cannel
IDEC PEB 2075
R
ITB05392
Figure 1 Application Example for a PBX
Semiconductor Group 6 01.96
PEB 2096
SICOFI(R)-4 The programmable Signaling and CODEC Filter with 4 channels, PEB 2465, implements 4 t/r (a/b) interfaces to link analog voice terminals to PBX subscriber lines or analog PBX trunk lines to public switches. An integrated Digital Signal Processor handles all the algorithms necessary, e.g. transhybrid-loss adaption, gain, frequency response, impedance matching. The IOM-2 Interface handles digital voice transmission, SICOFI-4 feature control and transparent access to the SICOFI-4 command and indication pins. To program the filters, precalculated sets of coefficients are downloaded from the system to the on-chip coefficient RAM. Thus it is possible to use the same line card in different countries. The SICOFI-4 is a CMOS device offered in a P-MQFP-64 package. ISDN-Oriented Modular Interface (IOM(R)-2) The IOM-2 interface is a four-wire interface which has been defined by the "Group of Four": ALCATEL, Siemens, Plessey and ITALTEL systems houses. It became a standard interface for interchip communication in ISDN applications. All ICs described above are compatible to the IOM-2 interface and operate from a single 5 V power supply (incl. SICOFI-4).
Semiconductor Group
7
01.96
Octal Transceiver for UPN Interfaces OCTAT-P
PEB 2096
Version 1.3 1.1 Features
CMOS
* Eight full duplex 2B+D UPN interface transceivers, each equipped with the following functions: - Conversion from/to binary to/from pseudo-ternary code - Receive timing recovery - Activation/deactivation procedures, triggered by primitives received over the IOM interface or by P-MQFP-44 INFO received from the line (e.g. detection of INFO 1) - Execution of test loops - Analog line transceiver for up to 16 dB line attenuation - UPN interface functions compatible to PEB 2095, IBC, and PEB 20950, ISAC-P (except for looplength) - UPN interface fully compatible to PSB 2196, ISAC-P TE, and PSB 2197, SmartLink-P. * IOM-2 interface * Support for JTAG boundary scan test * 1 CMOS technology with low power consumption * P-MQFP-44 package
Note: UPN refers to a version of the standard interface UP0 (according to ZVEI standard) with a reduced loop length (up to 1.3 km).
Type PEB 2096
Semiconductor Group
Ordering Code Q67100-H6422
8
Package P-MQFP-44
01.96
PEB 2096
1.2
Logic Symbol
Figure 2
Semiconductor Group 9 01.96
PEB 2096
1.3
Pin Configuration (top view)
P-MQFP-44
Figure 3
Semiconductor Group 10 01.96
PEB 2096
1.4 Pin No.
Pin Definitions and Functions Symbol Input (I) Output (O) I I Function + 5 V power supply Reference ground UPN Line Interfaces a,b No. 0: differential input / output No. 1: differential input / output No. 2: differential input / output No. 3: differential input / output No. 4: differential input / output No. 5: differential input / output No. 6: differential input / output No. 7: differential input / output IOM(R)-2 Interface Frame Synchronization Clock: 8 kHz Data Clock Data Downstream (data input) Data Upstream (data output) Interface Data rate Select (static pin-strapped): 0: double DCL (normal IOM interface) 1: single DCL JTAG Boundary Scan Interface Test Mode Select, internal pull-up resistor Test Clock Test Data Input, internal pull-up resistor Test Data Output Oscillator or 15.36 MHz clock input Oscillator output Clock output 15.36 MHz (i.e. to drive other OCTAT-P) Clock output 7.68 MHz (i.e. to drive ISAC-S or QUAT-S) Reset, active high
6, 12, 22, 28, VDD 34, 44 VSS 3, 9, 19, 25, 31, 37 33, 32 30, 29 27, 26 24, 23 1, 2 4, 5 7, 8 10, 11 43 42 41 40 39 LI0a,b LI1a,b LI2a,b LI3a,b LI4a,b LI5a,b LI6a,b LI7a,b FSC DCL DD DU IDS
I/O I/O I/O I/O I/O I/O I/O I/O I I I O I
16 15 14 13 20 21 36 35 38
TMS TCK TDI TDO XTAL1 XTAL2 CLK1 CLK2 RST
I I I O I O O O I
Semiconductor Group
11
01.96
PEB 2096
1.4 Pin No. 18 17
Pin Definitions and Functions (cont'd) Symbol Input (I) Output (O) SSYNC MODE I I Function Superframe synchronization This pin selects the initial values of the General Configuration Register and in the Configuration Register for UPN Line Interfaces as described in chapters 4.2 and 4.4. It also enables Push-Pull Sensing on pin DU as described in chapter 3.3.
Semiconductor Group
12
01.96
PEB 2096
1.5
Block Diagram
Figure 4
Semiconductor Group 13 01.96
PEB 2096
2
Functional Description
The PEB 2096, OCTAT-P, performs the layer-1 functions of the ISDN basic access for eight UPN interfaces at the LT side of the PBX. 2.1 * * * * * Device Architecture
The OCTAT-P contains the following functional blocks: Refer to figure 4 Eight line transceivers for the UPN interfaces One IOM-2 interface Frame structure converter between the IOM-2 interface and the UPN interfaces JTAG Boundary scan interface Clocking, reset and initialization block Interfaces General Principle of the U PN Interface
2.2 2.2.1
A frame transmitted by the exchange (LT) is received by the terminal equipment (TE) after a given propagation delay (td). Refer to figure 5. The terminal equipment waits a minimum guard time (tg = 5.2 s) while the line clears. It then transmits a frame to the exchange. The exchange begins a transmission every 250 s (known as the burst repetition period). However, the time between the reception of a frame from the TE and the beginning of transmission of the next frame by the LT must be greater than the minimum guard time. Communication between an LT and a PT (Private Termination) follows exactly the same procedure. Note that the guard time in TE is always defined with respect to the M-bit.
Semiconductor Group
14
01.96
PEB 2096
tr
LT
TE/PT
td
tg
td
LF 1
B1 8
B2 8
D 4 99 s LF-Framing Bit
B1 8
B2 8
M1) DC 2) 1 #Bits
1)
M Channel Superframe
CV T S T CV T S T CV
ITD00823
CV = Code Violation: for Superframe synchronization t = Transparent Channel (2 kbit/s) S = Service Channel (1 kbit/s)
2)
DC balancing bit, only sent after a code violation in the M-bit position and in special configurations. Timings: t r =burst repetition period = 250 s t d =line delay = 20.8 s maximum t g =guard time = 5.2 s minimum
Figure 5 UP0 Interface Frame Structure (= UPN) Within a burst, the data rate is 384 kbit/s. The 38-bit frame structure is as shown in figure 5. The framing bit (LF) is always logical `1'. The frame also contains the user channels (2B + D). It can readily be seen that in the 250 s burst repetition period, 4 D bits, 16 B1 bits and 16 B2 bits are transferred in each direction. This results in an effective full duplex data rate of 16 kbit/s for the D channel and 64 kbit/s for each B channel. The final bit of the frame is called the M bit. Its data rate is 4 kbit/s. Four successive M bits, from four successive U frames, constitute a superframe. Three signals are carried in this superframe. Every fourth M bit is a code violation (CV) and is used for superframe synchronization. This can be regarded as the first bit of the superframe.
Semiconductor Group 15 01.96
PEB 2096
From this reference (CV = bit 1), bit 3 of the superframe is the service channel bit S. This S-channel bit is transmitted once in each direction in every fourth burst repetition period. Hence the duplex S channel has a data rate of 1 kbit/s. It conveys test loop control information from the LT to the TE/PT and reports of transmission errors from the TE/PT to the LT. Bit 2 and bit 4 of the superframe are the T bits. This 2 kbit/s channel is accessible via the C/I channel and may be used to carry the "available"/"blocked" information sent by the D-channel arbiter of the PEB 20550, ELIC. It is allowed to add a DC balancing bit to the burst, in order to decrease DC offset voltage on the line after transmission of a CV in the M-bit position. The OCTAT-P transmits this DC balancing bit when transmitting INFO 4 and when line characteristics indicate potential decrease in performance. The OCTAT-P scrambles B-channel data on the UPN interface in order to ensure that the downstream receiver (e.g. ISAC-P TE) gets enough pulses for a reliable clock extraction (flat continuous power density spectrum is provided) and no periodic patterns appear on the line. The scrambling is in accordance with CCITT V.27. The coding technique used on the U interface is a half-bauded AMI code (with a 50 % pulse width). A logical `0' corresponds to a neutral level, logical `1' are coded as alternate positive and negative pulses. Code violation (CV) is caused by two successive pulses with the same polarity. See figure 6. The AMI coding includes always the data bits going on the UPN interface in one direction. Thus there is a separate AMI coding unit for data downstream and one for data upstream.
Figure 6 AMI Coding on the UPN Interface
Semiconductor Group 16 01.96
PEB 2096
2.2.2
IOM(R)-2 System Interface
The PEB 2096, OCTAT-P, is equipped with a digital ISDN Oriented Modular (IOM-2) interface, for communication with upper layer functions, such as IDEC (PEB 2075), EPIC (PEB 2055) and ELIC (PEB 20550). EPIC and ELIC represent the first switching stage towards the exchange system. Refer to figure 7.
Figure 7 System Integration, IOM(R) Interface The IOM interface is a four-wire serial interface with a data clock (DCL), an 8 kHz frame synchronization clock (FSC), and one data line per direction: data downstream (DD) and data upstream (DU). One IOM-2 frame consists of up to 8 IOM channels (subframes) (figure 8).
Semiconductor Group 17 01.96
PEB 2096
125 s FSC DCL DU DD
IOM CH0 IOM CH0
R
R
CH1 CH1
CH2 CH2
CH3 CH3
CH4 CH4
CH5 CH5
CH6 CH6
CH7 CH7
CH0 CH0
B1
B2
MONITOR
D
C/I
MM RX
ITD04319
Figure 8 Multiplexed Frame Structure of the IOM(R)-2 Interface in LT-Mode with 2.048 Mbit/s Data Rate Each IOM channel consists of a total of 32 bits, or four octets: B1 + B2 + D (18 bits) plus 14 overhead bits for monitor and control information (activation/deactivation of OSI layer-1 and maintenance functions). The ISDN user data rate is 144 kbit/s (B1 + B2 + D). The data is transmitted transparently synchronous and in phase in both directions over the IOM interface using time division multiplexing within the 125 s IOM-2 interface frame. Nominal bit rate of data (DD and DU): Nominal frequency of DCL: Nominal frequency of FSC: 256 kbit/s 512 kHz 8 kHz ... 4096 kbit/s ... 8192 kHz
Note: The bit rate must be a multiple of 256 kbit/s.
Semiconductor Group 18 01.96
PEB 2096
In order to allow the use of the eight channels also with a maximum clock rate of 2,048 kHz provided by the system, the OCTAT-P can also run the IOM interface with only half the nominal DCL clock rate, i.e. 2,048 kHz for 2,048 kbit/s (Input pin IDS = 1). The OCTAT-P requires three IOM frames to synchronize to the DCL frequency. A corrupted IOM frame caused by different amount of DCL pulses within two consecutive IOM frames (e.g. caused by spikes on DCL or FSC) resets internally all registers and the activation and deactivation state machine, figure 21. The allocation between UPN line interfaces and the IOM-2 interface channels is according to their numbers, i.e. LI0a,b is allocated to IOM channel 0, LI1 to channel 1, and so on. For details refer to figures 14 and 15 and to the chapter 5.8 and the IOM Interface Specification, Rev. 2. Monitor Channel The monitor channel is used to convey messages (e.g. when a bit error occurs on UPN) or for access to internal registers: Identification Register, General Configuration Register, Bit Error Register, Configuration Register for U PN and Test Registers. The PEB 2096, OCTAT-P, has implemented the monitor channel protocol according to the IOM Interface Specification, Rev. 2, in the first of the eight IOM channels allocated to the eight UPN interfaces. Refer also to the chapter 3.7. C/I-Channel The C/I-channel is used for communication between the PEB 2096, OCTAT-P, and a processor via a layer-2 device, to control and monitor layer-1 functions. The OCTAT-P has 8 IOM-2 channels and thus 8 C/I-channels; one for each transceiver. The codes originating from layer-2 devices are called "commands", those from the PEB 2096, OCTAT-P, are called "indications". For a list of the C/I (command/indication) codes and their use, refer to the chapters 3.8. 2.2.3 JTAG Boundary Scan Test Interface
The OCTAT-P provides fully IEEE Standard 1149.1 compatible boundary scan support to allow cost effective board testing. It consists of: * * * * * Complete boundary scan test Test access port controller (TAP) Four dedicated pins (TCK, TMS, TDI, TDO) One 32-bit IDCODE register Specific functions for LIna,b
Semiconductor Group
19
01.96
PEB 2096
2.2.3.1 Boundary Scan Test The following OCTAT-P pins are included in the boundary scan: CLK2, CLK1, RST, IDS, DU, DD, DCL, FSC, MODE, SSYNC, XTAL1. Three additional user specific instruction codes control the transmission of continuous pulses at the line interface LIna,b. Depending on the pin functionality one or two boundary scan cells are provided. Pin Type Input Output Number of Boundary Scan Cells 1 2 Usage Input Output, enable
When the TAP controller is in the appropriate mode data is shifted into/out of the boundary scan via the pins TDI/TDO using a 6.25 MHz clock on pin TCK. The OCTAT-P pins are included in the following sequence in the boundary scan: Boundary Scan Boundary Scan Number TDI --> 1 2 3 4 5 6 7 8 9 10 11 Pin Number Pin Name Type Number of Scan Cells 2 2 1 1 2 1 1 1 1 1 1
35 36 38 39 40 41 42 43 17 18 20
CLK2 CLK1 RST IDS DU DD DCL FSC MODE SSYNC XTAL1
O O I I O I I I I I I
Semiconductor Group
20
01.96
PEB 2096
2.2.3.2 TAP Controller The Test Access Port (TAP) controller implements the state machine defined in the JTAG standard IEEE St. 1149.1. Transitions on the pin TMS cause the TAP controller to perform a state change. The TAP controller supports 8 instructions: * 5 instructions following the standard definition and * 3 user specific instructions. Code 0000 0001 0010 0011 11xx 1001 1010 1011 Instruction EXTEST INTEST SAMPLE/PRELOAD IDCODE BYPASS User specific User specific User specific Function External testing Internal testing Snap-shot testing Reading ID code register Bypass operation Continuous pulses on LIna and LInb Continuous pulses on LIna Continuous pulses on LInb
EXTEST is used to examine the board interconnections. When the TAP controller is in the state "update DR", all output pins are updated with the falling edge of TCK. When it has entered state "capture DR" the levels of all input pins are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically done using the instruction SAMPLE/PRELOAD. INTEST supports internal chip testing. When the TAP controller is in the state "update DR", all inputs are updated internally with the falling edge of TCK. When it has entered state "capture DR" the levels of all outputs are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically done using the instruction SAMPLE/PRELOAD.
Note: 0011 (IDCODE) is the default value of the instruction register.
SAMPLE/PRELOAD provides a snap-shot of the pin level during normal operation or is used to preload (TDI) / shift out (TDO) the boundary scan with a test vector. Both activities are transparent to the system functionality.
Note: The input pin XTAL1 should not be evaluated. The input frequency (15.36 MHz) is not synchronous to TCK (6.25 MHz) which causes unpredictable snap-shots on the pin XTAL1.
Semiconductor Group
21
01.96
PEB 2096
IDCODE The 32-bit identification register is serially read out via TDO. It contains the version number (4 bits), the device code (16 bits) and the manufacture code (11 bits). The LSB is fixed to "1". Code for the Version 1.3 is "0010" (Version 1.2: "0001"). Version 0010 Device Code 0000 0000 0001 0100 Manufacture Code 0000 1000 001 1 Output --> TDO
Note: In the state "test logic reset" the code "0011" is loaded into the instruction code register.
BYPASS, a bit entering TDI is shifted to TDO after one TCK clock cycle, e.g. to skip testing of selected ICs on a printed circuit board.
Semiconductor Group
22
01.96
PEB 2096
User Specific Instructions Three different user specific pulse types are selectable, figure 9. An oscillator with a 15.36 MHz clock or an external clock is necessary for 192 kHz test pulse generation; according to the instruction code 9H.
Figure 9 Test Pulse Wave Forms
Semiconductor Group
23
01.96
PEB 2096
2.3 2.3.1
Individual Functions Transceiver, Analog Connections
The receiver input stages consist of an amplifier/equalizer, followed by a peak detector adaptive controlling the thresholds of the comparators and a digital oversampling unit.
Figure 10 Transceiver Functional Blocks
External to the line interface pins LIna,b are connected: a transformer, external resistors and two capacitors (100 nF and 0.33 F). Voltage overload protection is achieved by adding clamping diodes. Depending on the transformer ratio employed (2:1 or 1.25:1), the resistor values have to be chosen and the resistors have to be connected accordingly: Figure 11 depicts the analog connections for a transformer with the ratio 2:1 and figure 12 depicts the analog connections for a transformer with the ratio 1.25:1.
Semiconductor Group
24
01.96
PEB 2096
Figure 11 Transceiver with a 2:1 Transformer
Figure 12 Transceiver with a 1.25:1 Transformer
Semiconductor Group 25 01.96
PEB 2096
The PEB 2096, OCTAT-P, covers the electrical requirements of the UPN interface for loop lengths depending on the used transformer and the cable quality: a) If the equalizer is enabled (EQUDIS in Configuration Register for UPN Line Interface is set to low) Transformer 2:1 Cable J-Y (ST) Y 2 x 2 x 0.6 AWG 26 b) If the equalizer is disabled (EQUDIS in Configuration Register for UPN Line Interface is set to high) Transformer 2:1 Cable J-Y (ST) Y 2 x 2 x 0.6 AWG 26 Loop Length up to 0.8 km up to 1.3 km Loop Length up to 1 km up to 1.3 km
Concerning the 1.25:1 transformer, the maximum line attenuation is decreased by 3 dB.
Note: The actual values of the external resistors depend on the selected transformer. The resistor values in figures 11 and 12 are optimal for an ideal transformer (RCu = 0).
2.3.2 Transmit PLL
The transmit PLL (XPLL) synchronizes a 768 kHz transmit clock derived from the oscillator clock to FSC (8 kHz). When the oscillator clock is synchronous to FSC (fixed divider ratio of 1920 from 15.36 MHz clock) the XPLL will not perform any tracking after having locked the phase, i.e. the input jitter on clocks XTAL and FSC will not be increased. Alternatively, when a free running oscillator is used, XPLL tracking increases FSC jitter by 32.5 ns (half oscillator period). 2.3.3 Receive PLL
The receive PLL (RPLL) recovers bit timing from a comparator output signal. The comparator has a threshold of 90 % with respect to the signal stored by the peak detector. The RPLL performs PLL tracking after detecting phase shifts of the same polarity in four pulses. A phase adjustment is done by adding or substracting 65 ns (one oscillator period) to or from the 384 kHz receive clock.
Semiconductor Group
26
01.96
PEB 2096
2.3.4
Receive Signal Oversampling
In order to additionally reduce the bit error rate in severe conditions, the OCTAT-P performs oversampling of the received signal and uses majority decision logic. As illustrated in figure 13, each received bit is sampled 6 times at 15.36 MHz clock intervals inside the estimated bit window. The samples obtained are compared against a threshold of 50 % with respect to the signal stored by the peak detector. If at least 4 samples have an amplitude exceeding the 50 % threshold, a logical "1" is considered to be detected; otherwise a logical "0" (no signal) is considered to be detected
.
Figure 13 UPN Receive Signal Oversampling
Semiconductor Group 27 01.96
PEB 2096
2.3.5
Activation / Deactivation
An incorporated finite state machine controls the activation and deactivation procedures and communicates with the layer-2 unit via the IOM-2 C/I channel. Each of the eight C/I channels is allocated to its corresponding line interface. 2.3.6 Diagnostic Functions
Loop 2 is activated over the IOM interface with Activate Request Loop 2 (AR2). The loop will be closed in the TE after detection of the associated bit in the UPN maintenance bit (S-bit). Loop 1 is activated over the IOM interface with Activate Request Loop 1 (ARL). No UPN line is required. Info 4 is looped back to the receiver and also sent to the UPN interface. When the receiver is synchronized, the message "AI" is sent in the C/I channel.
Semiconductor Group
28
01.96
PEB 2096
3 3.1
Operational Description General
All procedures required for data transmission over the UPN interface are implemented. These comprise the UPN interface frame and multiframe synchronization, activation/deactivation procedure, and timing requirements such as bit rate and jitter. The internal finite state machine of the PEB 2096, OCTAT-P, controls the activation/deactivation procedures, switching of loops and transmission of special pulse patterns. Such actions can be initiated by signals on the UPN transmission line (INFO's) or by control (C/I) codes sent over the IOM interface. Refer to figure 21. The exchange of control information in the C/I channel is state oriented. This means that a code in the C/I channel is repeated in every IOM frame until a change is necessary. A new code must be found in two consecutive IOM frames to be considered valid (double last look criterion). The monitor channel is used to convey message oriented information. This means that an information in the monitor channel is transferred once, and the receiver stores that message. In order to ensure safe data transfer, a handshake procedure between monitor channel transmitter and receiver is necessary. An example show figures 19 and 20. For details refer to the IOM-2 Interface Specification, Rev. 2. 3.2 Clocking, Reset and Initialization
At power up, a reset pulse (RST) should be applied to force the line interfaces of the PEB 2096, OCTAT-P, to the state "reset". No clocks are required during that procedure. The pin SSYNC must be set to VDD if not used. After that the line interfaces of the PEB 2096, OCTAT-P, may be operated according to the state diagram (figure 21), each controlled via the corresponding C/I channel. 3.3 Push - Pull Sensing on Pin DU
The OCTAT-P supports configurations where multiple ICs are connected to the IOM-2 interface. If the MODE pin is connected to VDD the OCTAT-P senses after reset whether an external pull-up resistor is connected to pin DU or not. If no resistor is detected the pin DU is changed to push-pull. If a resistor is detected the pin DU is changed to open drain. The sensing is done within 2 consecutive IOM frames at bit position 15 (last bit of B2 channel). The pin DU is always push-pull if the MODE pin is connected to VSS.
Semiconductor Group
29
01.96
PEB 2096
3.4
Transmit Delay on UPN Interface in respect to IOM(R)-2 Interface
The OCTAT-P causes delays of B- and on D-channels with respect to the IOM channel number. Figure 14 shows this delay at a data rate of 2.048 Mbit/s.
.
Figure 14 Transmit Delay of B- and D-Channels
Semiconductor Group
30
01.96
PEB 2096
3.5
UPN Multiframe Synchronization
There are two possibilities how to synchronize the UPN multiframe: With a short FSC or with SSYNC. 3.5.1 Synchronization with a Short FSC
The short FSC pulse has a width of one DCL clock (in normal use the FSC is at least 2 DCL wide). The SSYNC input must be set to 1. The period of the short FSC pulses must be a multiple of 1 ms. The UPN frame with a code violation in the M bit starts in the IOM channel 0 which follows the short FSC pulse. Refer to figure 15.
Figure 15 Synchronization with a short FSC 3.5.2 Synchronization using SSYNC (for DECT)
A zero pulse on the SSYNC input forces the OCTAT-P to start a multiframe with a code violation in the next M-bit. Refer to figure 16.
Figure 16 Synchronization with SSYNC While using SSYNC for UPN multiframe synchronization the short FSC signal is not allowed. If the bit SYNEN is set (Configuration Register, bit 7) the zero pulse on SSYNC forces the OCTAT-P also to set the T bit in the next UPN frame. If not used the SSYNC input must be connected to VDD.
Semiconductor Group 31 01.96
PEB 2096
3.6
D-Channel Handling
Decentralized D-Channel processing can be realized by the use of only one multiplexed HDLC-Controller, which is integrated with a D-channel Arbiter in the ELIC, PEB 20550. Typically the D-channel load has a very bursty characteristic. Taking this into account, the ELIC provides the capability to multiplex one HDLC-controller among several subscribers. This feature results in a drastical reduction of hardware requirements while maintaining all benefits of HDLC based signaling (figure 17). A D-channel arbiter is used to assign the receive and transmit HDLC-channels independently to the subscriber terminals. In downstream direction the arbiter links the transmit channel to one or more (broadcast) programmable IOM-2 D-channels (ports). In upstream direction the arbiter assigns the HDLC-receive channel to a requesting subscriber and indicates to all other subscribers that their D-channels are blocked, using a control channel. This configuration supports full duplex layer-2 protocols with bus capability e.g. LAPD or proprietary implementations. Consequently no polling overhead is necessary providing the full 16-kbit/s bandwidth of the D-channel for data exchange.
B Channels
IOM -2 Interface
R
EPIC
R
PCM Highway
D Channel Controlling D Channel ARBITER SACCO CH-A
P
SACCO CH-B ELIC
R
Signaling Highway
ITS05808
Figure 17 D-Channel Handling with only one Multiplexed HDLC-Controller (SACCO-A)
Semiconductor Group 32 01.96
PEB 2096
The control channel is unidirectional and forwards the status information of the corresponding D-channel (blocked or available) towards the subscriber terminal. Different existing channel structures are used to implement the control channel between the HDLC-controllers on the line card and in the subscriber terminal. Control Channel Implementation on the U PN-Interface On UPN-line card, the control channel is integrated in the C/I-channel. The OCTAT-P uses the T-channel to transmit the control channel information to the terminal. The T-channel is a subchannel of the UPN-interface with a bandwidth of 2 kbit/s. In the subscriber terminal the control channel is included again in the IOM-2 interface. Depending on the terminal configuration two alternatives can be selected in the terminal transceiver device. The blocked/available information is translated directly into the S/G-bit (Stop/Go) when no subsequent transceiver circuit is present in the terminal. The S/G-bit is evaluated by the terminal HDLC-controller ICC. It stops data transmission immediately when the S/G-bit is set to 1. When an additional transceiver device is integrated in the terminal (e.g. an S0-adapter, PEB 2081 (SBCX)) the control channel is translated into the A/B-bit. The A/B-bit is monitored by the SBCX. A/B = 1 indicates that the corresponding D-channel is available (A/B = 0 blocked). Depending on this information, the SBCX controls the E-bit on the S0-bus and the S/G-bit on the IOM-2 interface. When A/B = 0 the E-bit is forced in the inverted D-bit state, the S/G-bit is set to high. As a result all active transmitters in the terminal and on the S0-bus are forced to abandon their messages.
Semiconductor Group
33
01.96
PEB 2096
Figure 18 Control Channel Implementation with OCTAT(R)-P (PEB 2096) as Line Card Transceiver and S0-Adapter.
Semiconductor Group 34 01.96
PEB 2096
3.7
IOM(R)-2 Interface Monitor Channel
The monitor channel is used to convey message oriented information. This means that an information in the monitor channel is transferred once, and the receiver stores that message. There is a defined handshake procedure between the monitor channel transmitter and the receiver in order to ensure a safe data transfer over the IOM-2 interface. The OCTAT-P uses the monitor channel of IOM channel 0 for local programming and reading (register access). The monitor channel operates on an asynchronous basis. While data transfer on the bus takes place synchronized to frame sync, the data flow is controlled by a handshake procedure using the monitor channel receive bit (MR) and the monitor channel transmit bit (MX). For example: data is placed onto the monitor channel and the MX bit is activated (active low). This data will be transmitted repeatedly once per 8 kHz frame until the transfer is acknowledged via the MR bit. The monitor channel is in an idle condition when the MX bit is inactive in two or more consecutive frames (indication of End Of Message EOM). Before starting a transmission to the OCTAT-P, the microprocessor should verify that the transmitter of the OCTAT-P is inactive, i.e. that a previous transmission has been terminated. The OCTAT-P has a monitor transmitter time-out function of minimum 4 ms implemented. This prevents the monitor message to be transmitted continuously if the monitor data won't be acknowledged by the receiver. An example for a P, ELIC and OCTAT-P communication is shown in figures 19 and 20. First the Identification Register of the OCTAT-P may be read. Two bytes are transmitted to the OCTAT-P and as a result of the read operation two bytes are returned to the controller. In case of a write operation the data are only acknowledged and no data are returned from the OCTAT-P to the controller. The first byte of the data transmitted to the OCTAT-P always indicates the type of the desired monitor operation (i.e. read or write to the internal registers). The example shows the typical register access of the ELIC and gives a feeling about the important bits. The ELIC uses a 16-byte FIFO for transmission and reception of the monitor data. Therefore the user doesn't need to provide routines for the handshake protocol.
Semiconductor Group
35
01.96
PEB 2096
Figure 19 Monitor Channel Handling: P ELIC OCTAT-P
Semiconductor Group 36 01.96
PEB 2096
A detailed description of the hand-shake procedure using MX and MR bits is shown on figure 20.
Figure 20 Monitor Channel Handling: Hand-shake by the Use of MX and MR Bits
Semiconductor Group 37 01.96
PEB 2096
3.8
Command / Indicate Channel
The C/I channel is used for communication between the OCTAT-P and a layer-2 device (or ELIC), to control and monitor layer-1 functions. The layer-2 device monitors the layer-1 indication continuously and indicates a change if a new code is found to be valid in two consecutive IOM frames (double last look criterion). Table 1 Commands Command (downstream) Abbr. Code Remarks Deactivate request Reset Test mode 2 Test mode 1 Activate request = "available" DR RES TM2 TM1 AR 0000 0001 0010 0011 1000 1010 1001 1100 1111 Transmission of pseudo-ternary pulses at 2 kHz frequency Transmission of pseudo-ternary pulses at 192 kHz frequency Transmission of INFO 2 or INFO 4, T bit set to one Transmission of INFO 2, switching of loop 2 (at TE), T bit set to one Transmission of INFO 2, switching of loop 1 (on U interface), T bit set to one Transmission of INFO 4, T bit set to zero Deactivation acknowledgment, quiescent state
Activate request test loop 2 AR2 Activate request local test loop Activate indication = "blocked" Deactivate confirmation ARL AI DC
Semiconductor Group
38
01.96
PEB 2096
Table 2 Indications Indication (upstream) Timing required (to activate IOM-2) Resynchronization (loss of framing) Activate request U only activation indication Activate indication Deactivate indication Abbr. Code Remarks TIM RSY AR UAI AI DI 0000 0100 1000 0111 1100 1111 Deactivated state, activation from the line not possible Receiver is not synchronous Info 1w received Info 1 received synchronous receiver Layer-1 fully activated Info 0 or DC received after deactivation request
In PBX applications with decentral D-channel handling, all D-channels can be handled by a D-channel arbiter of the ELIC, PEB 20550; one signalling controller in multiplexer mode (SACCO-A) can be used for up to 32 ISDN subscribers. A terminal is allowed to send data only when the signalling controller is available and the subscriber was selected by the arbiter. The command C/I = 1000H indicates to the OCTAT-P that the selected D-channel can be used (is "available"), C/I = 1100H indicates that the D-channel currently can not be used as the signalling controller is allocated to an other terminal. The addressed D-channel is "blocked". The OCTAT-P controls the terminal transmitter (e.g. ISAC-P TE) accordingly. It translates the information whether the D-channel is "available" or "blocked" by setting the T-bit on the UPN interface. T = 1 indicates to the terminal (via the UPN transmitter) that it's HDLC controller can send data. T = 0 indicates that the HDLC controller can not send data or has to abort sending data.
Note: The two codes (C/I = 1000H and 1100H) can only be used when the OCTAT-P is in a state INFO 4 transmission.
Semiconductor Group
39
01.96
PEB 2096
3.9
Activation and Deactivation, State Machine
The activation and deactivation implemented in the PEB 2096, OCTAT-P, agree with the UP0 interface as implemented in the PEB 2095, IBC.
3.9.1
States Description
OCTAT-P state machine enters two different kind of states: Unconditional and conditional states, figure 21.
Semiconductor Group
40
01.96
PEB 2096
*)
refer to chapter 2.2
Figure 21 OCTAT-P State Diagram
Semiconductor Group 41 01.96
PEB 2096
Unconditional States Reset This state is entered unconditionally after a high appears on the RST pin, a corrupt IOM frame is acknowledged (if two subsequent IOM frames have different number of DCL clocks) or after the receipt of command RES (software reset). The analog section is disabled (transmission of INFO 0) and the UPN interface awake detector is inactive. Hence, activation from PT or TE is not possible. Test Mode The test signal (iti), sent to the UPN interface in this state is dependant on the command which originally invoked the state. TM2 causes single alternating pulses to be transmitted (it2); TM1 causes continuous alternating pulses to be transmitted (it1). The burst mode technique normally employed on the U interface is suspended in this state and the test signals are transmitted continuously. Pending Deactivation To access any of the conditional states from any of the above unconditional states the pending deactivation state must be entered. This occurs after the receipt of a DR command. In this state the awake detector is activated and the state is exited only when the line has settled (i.e. INFO 0 has been detected for 2 ms) or by the command DC.
Note: Although DR is shown as a normal command it can in fact be seen as an unconditional command. No matter which state the LT is in, the reception of a DR command will always result in the pending deactivation state being entered.
Conditional States Wait for DR This state is entered from the pending deactivation state once INFO 0 or DC has been identified. From here the line may be either activated, deactivated or a test loop may be entered. Deactivated This is the power down state of the physical protocol. The awake detection is active and the device will respond to an INFO 1w (wake signal) by initiating activation.
Semiconductor Group
42
01.96
PEB 2096
Pending Activation This state results from a request for activation of the line, either from the terminal (INFO 1w) or from the layer-2 device (AR, AR2 or ARL). Info 2 is then transmitted and the OCTAT-P waits for the responding INFO 1 from the remote device. Synchronized Upon receipt of INFO 1 the OCTAT-P must synchronize itself to the signal. This process takes at most 10 ms after which the OCTAT-P supplies INFO 2 to the remote terminal. It then synchronizes to the OCTAT-P. Activated Info 1 has a code violation in the framing bit (F bit) whereas INFO 3 has none. Upon the receipt of 2 frames without a code violation in the F bit, the OCTAT-P enters the activated state and outputs INFO 4. The line is now activated; the OCTAT-P sends INFO 4 to the remote, the remote sends INFO 3 to the OCTAT-P. Resynchronization If the OCTAT-P fails to recognize INFO 3, for whatever reason, it will attempt to resynchronize. Entering this state it will output INFO 2. This is similar to the original synchronization procedure in the pending activation state (the indication given to layer 2 is different). However as before, recognition of INFO 1 leads to the synchronized state. OCTAT-P state diagram is shown in figure 21. 3.9.2 Info Structure on the UPN Interface
Signals controlling and indicating the internal state of all UPN transceiver state machines are called INFOs. Four different INFOs (INFO 0, 1W, 1/2 and 3/4) can be sent over the UPN interface depending on the actual state (Synchronized, Activated, Pending Activation, Test Mode, Deactivated, Reset,...) of the connected transceivers (e.g. OCTAT-P and ISAC-P TE). When the line is deactivated INFO 0 is exchanged by the UPN transceivers at either end of the line. Info 0 indicates that there is no signal on the line; in either direction. When the line is activated INFO 3 (in upstream direction) and INFO 4 (in downstream direction) are continually sent. Info 3 and 4 contain the transmitted data (B1, B2, D, M).
Semiconductor Group
43
01.96
PEB 2096
Info 1w and 1/2 are used for initialization and tests. The form of all INFO is shown in the following table:
Name Info 0 Info 1W
Direction
Description
No signal on the line Upstream Downstream Upstream Asynchronous wake signal 2 kHz burst rate F0001000100010001000101010100010111111 Code violation in the framing bit (F) 4 kHz burst rate F000100010001000100010101010001011111M1)DC2) Code violation in the framing bit
Info 1
Upstream
Info 2
Downstream 4 kHz burst rate F000100010001000100010101010001011111M1) Code violation in the frame bit Upstream 4 kHz burst rate No code violation in the framing bit User data in B, D and M channels B channels scrambled, DC bit2) optional
Info 3
Info 4
Downstream 4 kHz burst rate No code violation in the framing bit User data in B, D and M channels B channels scrambled, DC bit2) optional
Note:
The M channel superframe contains: CV code violation [1 kbit/s (once in every fourth frame)] S bits transparent [1 kbit/s channel] T bits set to one [2 kbit/s channel] 2) DC balancing bit F = Framing bit
1)
Semiconductor Group
44
01.96
PEB 2096
3.9.3
Example of Activation and Deactivation
An activation and deactivation procedure between an OCTAT-P and an IBC or ISAC-P TE in TE mode over the UPN interface line is shown in figure 16. It illustrates how the state machines of the respective modes interwork to facilitate activation and deactivation. In this case activation was initiated by an AR request at the terminal side and deactivation by a DR command at the LT side. Activation could also be initialized at the LT side using an AR request.
Figure 22 Example for an ISAC(R)-P TE <---> OCTAT-P Activation and Deactivation
Note: T1: T2: T3: T4:
< 250 s < 10 ms 1 ms 2 ms
time for error free level detection time for synchronization four subsequent bursts with no CV in F bit time for error free detection of INFO 0
45 01.96
Semiconductor Group
PEB 2096
4
Registers Description
The monitor channel is used for programming local functions. It is implemented in OCTAT-P IOM channel 0 only. Accesses to the registers are treated as local functions and therefore are marked with the code "1000" in the first four bits of the message: Monitor message: Code = 1 0 0 0 Register Read An internal register is read by setting the internal address to zero (0H) and indicating the address of the specific register in the bits D(3:0). The bits D(7:4) are set to zero. E.g. "80H 01H" is the read command for the register 1H, the General Configuration Register. Code = 1 0 0 0 0000 0000 register addr.= 01H Internal address D7 D6 D5 D4 D3 D2 D1 D0
The response message from OCTAT-P comprises two bytes, the first showing the address after the local-function-code, the second showing the register data. E.g. "81H (D7:0)" is the response to a read command on address 1H, where D(7:0) is the content of the Configuration Register. Code = 1 0 0 0 Register Write An internal register is written by setting the internal address to the address of the specific register. The register will then be loaded with the value of D(7:0), e.g. "81H 5DH" programs the Configuration Register (addr. 1H) with the value 5DH. Code = 1 0 0 0 register addr. 0101 1101 register addr. = 01H D7 D6 D5 D4 D3 D2 D1 D0
Note: Hardware Reset or a corrupt IOM frame (refer to chapter 2.2.2) leads to the initial value of all writable registers.
4.1 Value: Description: Identification Register - (Read) 0H 00000100 The value of this register is specific for the PEB 2096, OCTAT-P.
Address:
Semiconductor Group
46
01.96
PEB 2096
4.2 Format:
bit 7 IC7D
General Configuration Register - (Write) 1H
Address:
bit 0 IC6D IC5D IC4D IC3D IC2D IC1D BEM
Initial Value: Description:
FFH 01H ICnD:
if the MODE pin is connected to VDD or if the MODE pin is connected to VSS IOM interface channel n disable (channel 1-7) 0...IOM channel n is enabled 1...IOM channel n is tristated Bit error mask 0...whenever the Bit Error Register value is unequal to zero, the register value is transmitted via the monitor channel 1...the Bit Error Register may be read, but there are no unsolicited monitor messages
BEM:
4.3 Format:
bit 7 BEO7
Bit Error Register - (Read) 1H
Address:
bit 0 BEO6 BEO5 BEO4 BEO3 BEO2 BEO1 BEO0
Initial Value: Description:
00H BEOn = 1: Bit error occurred on UPN line n. The Bit Error Register is reset after reading the register
Semiconductor Group
47
01.96
PEB 2096
4.4 Format:
bit 7
Configuration Register for UPN Line Interfaces - (Write) 2H
Address:
bit 0 BALEN EQUDIS 0 0 0 0 0
SYNEN
Initial Value: Description:
00H 20H SYNEN: BALEN: EQUDIS:
if the MODE pin is connected to VDD or if the MODE pin is connected to VSS SSYNC = low sets the first T bit in the superframe to high (refer to timing specification) Activates the DC balancing bit if INFO 4 (or 2) was transmitted. It is independent of the line performance. Disables the Equalizer when set to 1
4.5
Test Registers - (Read/Write)
Test registers are implemented in the address range of 8H to BH; they are not for customer use.
Semiconductor Group
48
01.96
PEB 2096
5 5.1
Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values 0 to 70 - 65 to 125 - 0.4 to VDD + 0.4 6 Unit C C V V
TA = 0 to 70 C; VDD = 5 V 5 %; VSS = 0 V
Parameter Ambient temperature under bias: PEB Storage temperature Voltage on any pin with respect to ground Maximum voltage on any pin
TA Tstg VS Vmax
Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Line Overload Protection The maximum input current (under voltage conditions) is given as a function of the width of a rectangular input current pulse. For the destruction current limits refer to figure 23.
Figure 23
Semiconductor Group
49
01.96
PEB 2096
Figure 24 Maximum Line Input Current 5.2 DC Characteristics
TA = 0 to 70 C; VDD = 5 V 5 %, VSS = 0 V
All pins except LIna,b; XTAL1, 2 Parameter L-input voltage H-input voltage L-output voltage H-output voltage H-output voltage Input leakage current Symbol Limit Values min. max. + 1.5 V V V V V V 1 A - 0.4 3.5 Unit Test Condition
VIL VIH VOL VOL1 VOH VOH ILI ILO
VDD + 0.4
0.45 0.45
2.4
VDD - 0.5
IOL = 2 mA IOL = 7 mA (DU only) IOH = - 400 A IOH = - 100 A 0 V VIN VDD 0 V VOUT VDD
All pins except: LIna, b; XTAL1,2; TDI; TMS
Semiconductor Group
50
01.96
PEB 2096
5.2
DC Characteristics (cont'd)
TA = 0 to 70 C; VDD = 5 V 5 %, VSS = 0 V All pins except LIna,b; XTAL1, 2
Parameter TDI; TMS Input leakage current high Input leakage current low LIna, b Operational supply current Symbol Limit Values min. max. 1 50 400 A A Unit Test Condition
ILIH ILIL
VIN = VDD VIN = 0 V; internal
pull-up resistor
ICC
50 + n x 2.8
mA
VDD = 5 V inputs at VSS/VDD, transformer
ratio 2:1 n = number of line interfaces activated, no output load at CLK, DU
Transmitter output impedance Receiver input impedance XTAL1 H-input voltage L-input voltage XTAL2 H-output voltage L-output voltage
7
30
k
ZR
10
IOUT = 20 mA VDD = 5 V VDD = 5 V; transmitter
stage inactive
VIH VIL
3.5 - 0.4
VDD + 0.4
1.5
V V
VOH VOL
VDD - 0.5
0.45
V V
IOH = 100 A, CLD 60 pF IOL = 100 A, CLD 60 pF
Semiconductor Group
51
01.96
PEB 2096
5.3
Capacitances
TA = 25 C; VDD = 5 V 5 %, VSS = 0 V
All pins except LIna, b Parameter Pin capacitance LIna,b Output capacitance against VSS XTAL1, 2 Motional capacitance Shunt Load Resonance resistor Symbol Limit Values min. max. 7 pF Unit Test Condition
CI/O
COUT
10
pF
Recommended typical crystal parameters. Refer to figure 18.
C1 C0 CL Rr
20 7 30 65
fF pF pF
Figure 25 Recommended Oscillator Circuits
Semiconductor Group 52 01.96
PEB 2096
5.4
AC Characteristics
TA = 0 to 70 C; VDD = 5 V 5 %
AC testing: Inputs are driven at VDD - 0.5 V for a logic "1" and 0.5 V for a logic "0". Timing measurements are made at 2.0 V for a logic "1" and at 0.8 V for a logic "0".
Figure 26 Jitter The clock input FSC is used as reference clock to provide the 768 kHz clock for the UPN interface. In the case of a plesiochronous 15.36 MHz clock generated by an oscillator with a maximum frequency deviation of 100 ppm, the clock FSC should have a jitter of less than 20 ns peak-to-peak, as the PLL manages max. 0.5 oscillator period (32.5 ns) in one IOM frame (in 125 s).
Semiconductor Group
53
01.96
PEB 2096
5.5 CLK1
Clocks
Parameter High phase of crystal/clock
Symbol
Limit Values min. max. 25
Unit Test Condition ns 50 pF load capacitance at CLK 50 pF load capacitance at CLK
tWH
Low phase of crystal/clock
tWL
25
ns
Clock period CLK2 Parameter High phase of crystal/clock
TP
65.08
65.12
ns
Symbol
Limit Values min. max. 57
Unit Test Condition ns 50 pF load capacitance at CLK 50 pF load capacitance at CLK
tWH
Low phase of crystal/clock
tWL
57
ns
Clock period
TP
130.16
130.24
ns
CLK2 is directly derived from the oscillator clock and can drive up to 6 oscillator inputs of the ISAC-S, PEB 2085.
3.5 V 0.8 V
t WH
TP
t WL
ITT00766
Figure 27 Definition of Clock Period and Width
Semiconductor Group 54 01.96
PEB 2096
5.6
Timing of the IOM(R) Interface
Figure 28 IOM(R) Interface Timing with Double Data Rate DCL
Semiconductor Group 55 01.96
PEB 2096
Parameter Frame sync. hold Frame sync. setup Frame sync. high Frame sync. low Data delay to clock Data setup Data hold Superframe sync. setup Superframe sync. hold Data clock high Data clock low
Symbol
Limit Values min. max. 30 70 130 TDCL 100 20 50 200 200 50 50
Unit ns ns ns ns ns ns ns ns ns ns
tFH tFS tFWH tFWL tDDC tDS tDH tSSYS tSSYH tDWH tDWL
Semiconductor Group
56
01.96
PEB 2096
Figure 29 IOM(R)-2 Interface Timing with Single Data Rate DCL
Semiconductor Group 57 01.96
PEB 2096
Figure 30 SSYNC Timing
Note: A low at SSYNC input sets the UPN superframe and forces the next transmitted T-bit to high if SYNEN is programmed to high.
5.7 Boundary Scan Timing Symbol Limit Values min. Test clock period Test clock period low Test clock period high TMS setup time to TCK TMS hold time from TCK TDI setup time to TCK TDI hold time from TCK TDO valid delay from TCK max. ns ns ns ns ns ns ns 60 ns 160 80 80 30 30 30 30 Unit
Parameter
tTCP tTCPL tTCPH tMSS tMSH tDIS tDIH tDOD
Semiconductor Group
58
01.96
PEB 2096
Figure 31 Boundary Scan Timing
Semiconductor Group
59
01.96
PEB 2096
5.8
UPN Frame Relation to FSC in Transmit Direction
The LF-bit on the UPN interface appears T0 after the last but two (3rd last falling edge) falling edge of DCL before FSC rising edge (figure 32).
Figure 32 F-bit Delay to FSC T0 = 85 oscillator periods + analog delay 0.5 oscillator periods Analog delay < 1 oscillator period (15.36 MHz)
Semiconductor Group
60
01.96
PEB 2096
5.9
Transceiver Characteristics
A detailed transceiver architecture is shown in figure 33. It comprises the transmitter output stages, the differential-to-single ended receiver input stage, the loop switch, the peak detector, and the threshold comparators.
Figure 33 Detailed Transceiver Architecture When transmitting a binary ONE, the transmitter output is 5 V (difference between LIna and LInb), when transmitting a binary ZERO, the transmitter output is in tristate. The receiver input range is from 5 V to 150 mV. The 150 mV level is a fixed minimum peak level.
Semiconductor Group 61 01.96
PEB 2096
Power Supply Rejection Ratio (PSRR) The PSRR of the receiver is better than - 40 dB at frequencies below 100 kHz, decreasing by 20 dB per decade above 100 kHz. Noise Immunity The noise immunity target of the receiver is better than 10 V/ Hz in the range up to 1 MHz, which should be achieved by both adaptive thresholds and digital oversampling techniques. Crosstalk Immunity The receiver immunity against crosstalk between neighbor receive channels, measured with minimum and maximum input levels at two neighbor inputs should not effect the overall transceiver performance according to the UP0 specification.
Semiconductor Group
62
01.96
PEB 2096
6
Package Outlines P-MQFP-44 (Plastic Metric Quad Flat Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 63
Dimensions in mm 01.96
GPM05622

▲Up To Search▲

Price & Availability of PEB2096

	To Download PEB2096 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .